IEEE

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

Abstract: In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry ...
Nature

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning ...
Nature

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to ...
IEEE

Implementation of radix 4 booth multiplier using MGDI technique

Abstract: Here we presents Modified Gate Diffusion Input technique used to implement radix 4 Booth Multiplier. Use of Booth algorithm as compare to other multiplication algorithms in multiplication ...
Frontiers

A biologically oriented algorithm for spatial sound segregation

Listening in an acoustically cluttered scene remains a difficult task for both machines and hearing-impaired listeners. Normal-hearing listeners accomplish this task with relative ease by segregating ...